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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
FEATURES:
* * * * * * * * * *
0.5 MICRON CMOS Technology Typical tsk(o) (Output Skew) < 250ps, clocked mode Low input and output leakage 1A (max) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 5V 10% Balanced Output Drivers: - 24mA (industrial) - 16mA (military) Series current limiting resistors Generate/Check, Check/Check modes Open drain parity error allows wire-OR Available in the following packages: - Industrial: SSOP, TSSOP - Military: CERPACK
DESCRIPTION:
The FCT162511T 16-bit registered/latched transceiver with parity is built using advanced dual metal CMOS technology. This high-speed, low-power transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The device has a parity generator/ checker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. Separate error flags exits for each direction with a single error flag indicating an error for either byte in the A-to-B direction and a second error flag indicating an error for either byte in the B-to-A direction. The parity error flags are open drain outputs which can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. The parity error flags are enabled by the OExx control pins allowing the designer to disable the error flag during combinational transitions. The control pins LEAB, CLKAB, and OEAB control operation in the A-to-B direction while LEBA, CLKBA, and OEBA control the B-to-A direction. GEN/ CHK is only for the selection of A-to-B operation. The B-to-A direction is always in checking mode. The ODD/EVEN select is common between the two directions. Except for the ODD/EVEN control, independent operation can be achieved between the two directions by using the corresponding control lines.
FUNCTIONAL BLOCK DIAGRAM
LEA B CLKAB Data 16 Parity GEN/CHK Byte Parity Generator/ Checker 2 Latch/ Register PERB (Open Drain) Parity, data 18 OEAB B0-15 PB1,2
A0-15 PA1,2 ODD/EVEN
LEB A CLKB A Parity, data 18 OEBA Latch/ Register Byte Parity Checking Parity, Data 18
PERA (Open Drain)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
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(c) 2001 Integrated Device Technology, Inc.
MAY 2001
DSC-2916/-
IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
BLOCK DIAGRAM
ODD/EVEN OEAB LEBA CLKB A CLKA B LEA B C A0 - A7 D C C D OEBA D C D B0 - B7
P
O
C D
C D P C D C D
PB1
PA1
I
C A8 - A15 D C
C D
B8 - B 15
C D D
P
O
C D
C D C D C D
PB2
PA 2
I
C GEN/CHK D C PER A (Open Drain) D
C D PERB (Open Drain) C D P
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
OEAB LEAB PA1 GND A0 A1 VCC A2 A3 A4 A5 A6 A7 GND PERA A8 A9 A10 A11 A12 A13 VCC A14 A15 GND PA2 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GEN/CHK CLKAB PB1 GND B0 B1 VCC B2 B3 B4 B5 B6 B7 PERB GND B8 B9 B10 B11 B12 B13 VCC B14 B15 GND PB2 CLKBA ODD/EVEN
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to 7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN CI/O CO Parameter(1) Input Capacitance I/O Capacitance Open Drain Capacitance Conditions VIN = 0V VOUT = 0V VOUT = 0V Typ. 3.5 3.5 3.5 Max. 6 8 6 Unit pF pF pF
PIN DESCRIPTION
Pin Names OEAB OEBA LEAB LEBA CLKAB CLKBA Ax Bx PERA PERB PAx
(1)
Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs Parity Error (Open Drain) on A Outputs Parity Error (Open Drain) on B Outputs A-to-B Parity Input, B-to-A Parity Output B-to-A Parity Input, A-to-B Parity Output Parity Mode Selection Input A to B Port Generate or Check Mode Input
PBx ODD/EVEN GEN/CHK
SSOP/ TSSOP/ CERPACK TOP VIEW
NOTE: 1. The PAx pin input is internally disabled during parity generation. This means that when generating parity in the A to B direction there is no need to add a pull up resistor to guarantee state. The pin will still function properly as the parity output for the B to A direction.
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1, 4)
Inputs OEAB H L L L L L L LEAB X H H L L L L CLKAB X X X L H Ax X L H L H X X Outputs Bx Z L H L H B(2) B(3)
FUNCTION TABLE (PARITY CHECKING) (1, 2, 3, 4)
A0 - A7 and PA1(5) Number of inputs that are high 1, 3, 5, 7 or 9 1, 3, 5, 7 or 9 0, 2, 4, 6 or 8 0, 2, 4, 6 or 8 ODD/EVEN L H L H PERB L H(6) H(6) L
NOTES: 1. A-to-B data flow is shown. B-to-A data flow is and CLKBA. 2. Output level before the indicated steady-state 3. Output level before the indicated steady-state provided that CLKAB was HIGH before LEAB 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance = LOW-to-HIGH Transition
similar but uses OEBA, LEBA, input conditions were established. input conditions were established, went LOW.
NOTES: 1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H. 2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses OEBA = L, OEAB = H and errors will be indicated on PERA. 3. In parity checking mode the parity bits will be transmitted unchanged along with the corresponding data regardless of parity errors (PB1 = PA1). 4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered clock. 5. Conditions shown are for the byte A0-A7 and PA1. The byte A8-A15 and PA2 is similiar. 6. The parity error flag PERB is a combined flag for both bytes A0-A7 and A8-A15. If a parity error occurs on either byte PERB will go low. PERB is an open drain output which must be externally pulled up to achieve a logic HIGH.
FUNCTION TABLE (PARITY GENERATION) (1, 2, 3, 4, 5)
A0 - A7 Number of inputs that are high 1, 3, 5 or 7 1, 3, 5 or 7 0, 2, 4, 6 or 8 0, 2, 4, 6 or 8 ODD/EVEN L H L H PB1 H L L H
NOTES: 1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H. 2. A-to-B parity checking is shown. B-to-A is capable of parity checking while A-to-B is performing generation. B-to-A will not generate parity. 3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered clock. 4. Conditions shown are for the byte A-A7. The byte A8-A15 is similiar but will output the parity on PB2. 5. The error flag PERB will remain in a high state during parity generation.
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL IIH Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) IIL Input LOW Current (Input pins)(5) Input LOW Current (I/O pins)(5) IOZH IOZL VIK IOS VH ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins)(5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Min., IIN = -18mA VCC = Max., VO = GND(3) -- VCC = Max. VO = 2.7V VO = 0.5V VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 -- -- -- -- -- -- -- -- -80 -- -- Typ.(2) -- -- -- -- -- -- -- -- -0.7 -140 100 5 Max. -- 0.8 1 1 1 1 1 1 -1.2 -250 -- 500 V mA mV A A Unit V V A
OUTPUT DRIVE CHARACTERISTICS
Symbol IODL IODH IOFF VOH VOL Output LOW Current Output HIGH Current Output Power Off Leakage Current (Open Drain)(5) Output HIGH Voltage (I/O pins) Output LOW Voltage (Open Drain) (I/O pins) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -16mA MIL IOH = -24mA IND IOL = 16mA MIL IOL = 24mA IND IOL = 48mA MIL IOL = 64mA IND
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C.
Parameter (I/O pins) (Open Drain)
Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3)
Min. 60 -- -60 -- 2.4 -- --
Typ.(2) 115 250 -115 -- 3.3 0.3 0.3
Max. 200 -- -200 1 -- 0.55 0.55
Unit mA mA mA A V V V
VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) VCC = 0, VO 5.5V
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) Test Conditions(1) All other Input Pins Parity Input Pins (PAx, PBx) VIN = VCC VIN = GND Min. -- -- -- Typ.(2) 0.5 1 75 Max. 1.5 2.5 120 A/ MHz Unit mA
VCC = Max. Outputs Open OEAB = GND, OEBA = VCC One Input Togging 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = GND, OEBA = VCC LEAB = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = GND, OEBA = VCC LEAB = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.8
1.7
mA
VIN = 3.4V VIN = GND
--
1.3
3.2
VIN = VCC VIN = GND
--
3.8
6.5(5)
VIN = 3.4V VIN = GND
--
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21.8(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (PROPAGATION DELAYS)
FCT162511AT Ind. Symbol tPLH tPHL tPLH tPHL tPLH(3) tPHL tPLH(3) tPHL tPLH tPHL tPLH(3) tPHL tPLH tPHL tPLH(3) tPHL tPZH tPZL tPHZ tPLZ tPLZ(3) tPZL tPLH(3) tPHL tPLH tPHL ODD/EVEN to PBx Parameter Propagation Delay, PAx to PBx Ax to Bx or Bx to Ax, PBx to PAx Propagation Delay Ax to PBx Propagation Delay Ax to PERB, PAx to PERB Propagation Delay Bx to PERA, PBx to PERA Propagation Delay LEBA to Ax and PAx LEAB to Bx and PBx Propagation Delay LEBA to PERA, LEAB to PERB Propagation Delay CLKBA to Ax and PAx CLKAB to Bx and PBx Propagation Delay CLKBA to PERA CLKAB to PERB Output Enable Time OEBA to Ax and PAx OEAB to Bx and PBx Output Disable Time OEBA to Ax and PAx OEAB to Bx and PBx Parity ERROR Enable OEBA to PERA, OEAB to PERB ODD/EVEN to PERx 1.5 1.5 1.5 1.5 1.5 6 6 10 10 10 1.5 1.5 1.5 1.5 1.5 6.3 6.3 10 10 10 1.5 1.5 1.5 1.5 1.5 6 6 10 10 10 1.5 1.5 1.5 1.5 1.5 6.3 6.3 10 10 10 ns ns ns ns ns 1.5 5.6 1.5 6 1.5 5.2 1.5 5.5 ns 1.5 6 1.5 6.5 1.5 5.6 1.5 5.8 ns 1.5 1.5 7 6 1.5 1.5 7 6 1.5 1.5 6 5 1.5 1.5 6.3 5.3 ns ns 1.5 5.6 1.5 6 1.5 5.3 1.5 5.5 ns 1.5 1.5 7 6 1.5 1.5 7 6 1.5 1.5 6 5 1.5 1.5 6.3 5.3 ns ns 1.5 5.6 1.5 6 1.5 5.3 1.5 5.5 ns GEN/CHK LOW Condition(1) CL = 50pF RL = 500 1.5 1.5 1.5 1.5 1.5 7.5 9 8 9 8 1.5 1.5 1.5 1.5 1.5 8 9 8 9 8 1.5 1.5 1.5 1.5 1.5 6.5 7.5 6.5 7.5 6.5 1.5 1.5 1.5 1.5 1.5 6.8 7.8 6.8 7.8 6.8 ns ns ns ns ns Min.(2) 1.5 Max. 5 Min.(2) 1.5 Mil. Max. 5.3 1.5 Ind. Min.(2) Max. 4.2 Min.(2) 1.5 FCT162511CT Mil. Max. 4.5 Unit ns
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. On Open Drain Outputs tPLH is measured at VOUT = VOL + 0.3V.
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (SET UP TIMES)
FCT162511AT Ind. Symbol tSU Parameter Set-up Time HIGH or LOW Ax to CLKAB tSU tSU Set-up Time PAx to CLKAB Set-up Time Bx to CLKBA, PBx to CLKBA tSU Set-up Time Ax to LEAB CLKAB LOW GEN/CHK LOW CLKAB LOW GEN/CHK HIGH CLKAB HIGH GEN/CHK LOW CLKAB HIGH GEN/CHK HIGH tSU Set-up Time PAx to LEAB CLKAB LOW GEN/CHK HIGH CLKAB HIGH GEN/CHK HIGH tSU Set-up Time Bx to LEBA PBx to LEBA tSK(O) Output Skew(4) CLKBA HIGH CLKBA LOW PBx valid PBx not valid PERB valid PERB not valid PBx valid PBx not valid PERB valid PERB not valid PERB valid PERB not valid PERB valid PERB not valid PERA valid PERA not valid PERA valid PERA not valid 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GEN/CHK HIGH GEN/CHK HIGH GEN/CHK LOW Test Conditions(1, 3) PBx valid PBx not valid PERB valid PERB not valid PERB valid PERB not valid PERA valid PERA not valid CL = 50pF RL = 500 4 3 4 3 4 3 4 3 -- -- -- -- -- -- -- -- 4 3 4 3 4 3 4 4 Mil. -- -- -- -- -- -- -- -- 3 3 3 3 3 3 3 3 FCT162511CT Ind. -- -- -- -- -- -- -- -- Mil. 3.5 3 3 3 3 3 3 3 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns Min. Max. Min. Max. Min. Max. Min. Max. Unit
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (HOLD TIMES)
FCT162511AT FCT162511CT Ind. Mil. Ind. Mil. Min. Max. Min. Max. Min. Max. Min. Max. Unit 1 -- 1 -- 1 -- 1 -- ns 1 -- 1 -- 1 -- 1 -- ns 1 -- 1 -- 1 -- 1 -- ns 1 -- 1 -- 0 -- 0 -- ns 1 -- 1 -- 0 -- 0 -- ns 3 -- 3 -- 3 -- 3 -- ns 3 -- 3 -- 3 -- 3 -- ns
Symbol tH tH tH tH tH tW tW
Parameter Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA Hold Time HIGH or LOW PAx to LEAB Hold Time HIGH or LOW PBx to LEBA Hold Time Ax to CLKAB, PAx to CLKAB Hold Time Bx to CLKBA, PBx to CLKBA LEAB or LEBA Pulse Width HIGH(2) CLKAB or CLKBA Pulse Width HIGH or LOW(2)
Condition(1) CL= 50pF RL = 500
NOTES: 1. See test circuits and waveforms. 2. This parameter is guaranteed but not tested. 3. "Not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the A to B or B to A port respective to the indicated direction. 4. Skew between any two outputs of the same package, switching in the same direction, excluding PERx in clocked mode, and Pxx (parity bits) and PERx in transparent/ latched mode. This parameter is guaranteed by design.
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V 500 V IN Pulse Generator D.U.T. 50pF RT 500 CL V OUT
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA INPUT tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE SAME PHA SE INPUT TRANSITION tPLH OUTPUT tPLH OPPOS ITE P HASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW SW ITCH CLOSED tPZH OUTPUT NORMALLY HIGH SW ITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ 1.5V 0V 3.5V VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT FCT XX Temp. Range XXX Family XXXX Device Type XX Package X Process Blank B Industrial MIL-STD-883, Class B Industrial Options Shrink Small Outline Package Thin Shrink Small Outline Package
PV PA
E
Military Options CERPACK
511AT 511CT
18-Bit Registered/Latched Transceiver
162 54 74
Double-Density, 5 Volt, Balanced Drive - 55C to +125C - 40C to +85C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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